Job Description

Role: Sr. STA Engineer

Exp: 6 - 12 years

Location: San Jose.

Full-time role. Onsite Opportunity.

Only US Citizens or Green Card Holders.

Role Summary:

We are seeking an experienced and highly skilled Sr. STA Engineer to join our team. The ideal candidate will bring deep expertise in timing analysis, digital and custom back-end flows.

Key Responsibilities:

Drive timing closure at the chip level and across hard macro boundaries.
Conduct advanced STA (Static Timing Analysis) with tools like PrimeTime (preferred) or Tempus.
Define and manage timing constraints, including SOCV/AOCV/POCV concepts, CTS, CDC timing, latch timing handling, and multi-cycle path optimization.
Collaborate on crosstalk noise analysis, signal integrity, and parasitic extraction to ensure robust designs.
Work with digital and custom back-end flows using tools such as Innovus, ICC2, and Virtuoso.
Lead and drive technical solutions across the organization, fostering collaboration and innovation.
Contribute to the design of memory interfaces (e.g., DDR4/5) and high-speed serial links (e.g., PCIe, USB, SATA, DisplayPort).
Utilize scripting languages (TCL, Perl, Makefiles) for design automation and process optimization.
Support device physics understanding as part of advanced design methodologies.

Required Skills & Experience:

Strong expertise in STA fundamentals, CTS, and CDC timing.
Proven experience with STA tools (PrimeTime preferred, Tempus accepted).
In-depth knowledge of SOCV/AOCV/POCV concepts and timing constraint management.
Hands-on experience driving timing closure at the chip and macro level.
Familiarity with crosstalk noise, signal integrity, and parasitic extraction.
Significant experience with digital/custom back-end tools (Innovus, ICC2, Virtuoso).
Proficiency in scripting languages like TCL, Perl, and Makefiles.

Job Tags

Full time,

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